Média
Partenaires
Recherche
Activités

Titre: Near-Threshold VLSI Circuits: a Route to Minimum-Energy Computing
Conférencier: Massimo Alioto , National University of Singapore, Singapore
Lieu: NEWCAS2014, Delta Trois-Rivières ,
Date et heure:
dimanche le 22 juin 2014 de 13:30 à 17:00

Résumé: In the last few years, near-threshold computing has gained a considerable attention from the industrial and academic community, thanks to the one-order of magnitude energy/power reduction that it can potentially enable. In particular, near-threshold circuits promise a more sustainable performance growth over the next CMOS technology generation for constant power envelope, as well as much more functionality on mobile devices. However, near-threshold circuits typically target 400-500 mV operation, which poses many challenges that need to be solved, before near-threshold integrated systems become viable for commercialization. Among those challenges, leakage comes back as crucial issue, since the related percentage of chip power can be easily 4-5X larger than that observed at nominal voltage (e.g., 1 V). Typically, 10X larger process/voltage/temperature variations challenge the robustness and ultimately the yield of nearthreshold systems, compared to nominal voltage. Moreover, the typical 10X performance degradation compared to nominal voltage requires rethinking architectures, as well as their interaction with circuit (down) and software level (up in the stack). Run-time techniques to detect/fix functional and soft failures need to be cohesively adopted at all levels of abstraction. In this tutorial, a survey of fresh ideas and very recent techniques to design near-threshold CMOS logic circuits and systems is presented. Emphasis is given on design solutions, and on the interaction between different levels of abstraction, since the above challenges need to be tackled at all levels of abstraction in a unitary manner. To give a unitary perspective, a few design principles are preliminarily introduced and then further developed for the main building blocks of Systems on Chip (processors, SRAM arrays, on-chip network and specialized hardware). The impact of sub-32nm technologies and the key design tradeoffs at near threshold are consistently exemplified by recent industrial and academic prototypes. Then, the tutorial explicitly addresses all key challenges, including energy efficiency, leakage and resiliency. Limits of current techniques to reduce leakage and dynamic energy are discussed, and fine-grain techniques are introduced as solution to improve the overall energy efficiency. Near-threshold-specific design flows are discussed and compared to traditional flows. Promising directions and future work are suggested at the end of the tutorial.

Note biographique: Massimo Alioto was born in Brescia in 1972. He took the M.Sc. degree in Electronic Engineering in 1997, and the Ph.D. degree in 2001 from the University of Catania. He is currently Associate Professor at the ECE department of the National University of Singapore. In 2002, he joined the Department of Information Engineering of the University of Siena as a Research Associate, where he became Assistant Professor (2002) and Associate Professor (2005). In the summer of 2007, he was visiting professor at EPFL – Lausanne (Switzerland). In 2009-2011, he was visiting professor at the Berkeley Wireless Research Center (BWRC) at the University of California, Berkeley. In 2011-2012, he is visiting professor at the University of Michigan, Ann Arbor. In 2013, he is visiting scientist at Circuit Research Lab – Intel Labs (Hillsboro, OR – USA). His research interests involve VLSI design from transistor to micro-architectural level, power harvesting/conversion/management in sub-mW systems and techniques for aggressive voltage scaling. He is author or co-author of more than 180 papers on international journals (65+, mostly IEEE Transactions) and international conferences. Two of them are among the 25 most downloaded IEEE TVLSI papers in 2007 (respectively the 10th and 13th). He is also coauthor of the book Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer). He is an IEEE Senior Member. He was Distinguished Lecturer by the IEEE Circuits and Systems Society for years 2009 and 2010. He regularly gives tutorials and keynote speeches at international conferences (ISCAS, ICECS, ICM, LASCAS), and seminars at universities and companies (IBM, Intel, Qualcomm). In 2010, he received the ISCAS 2010 Best Tutorial award for the tutorial “Pushing the Limits of Energy Consumption: Opportunities and Challenges in Subthreshold Logic” (an overview paper to TCAS-I was also invited, to open the 2012 editorial year). He was also Program Co-Chair for the IEEE Summer School on “Pushing the boundaries of energy efficiency in low power design”, held in Cuzco (Peru) in Jan. 17-21, 2011. He is Associate Editor-in-Chief of IEEE Transactions on VLSI Systems (2013 – present). He is/has been Associate Editor of numerous international journals.

Voyez tous les cour intensifs