Al-Khalili, Asim J.
Université Concordia
Membre régulier

Description du programme de recherche

Portable devices created new demands on VLSI architectures and circuits. The issue of power consumption and battery usage dictated the any necessity of circuits used to be more power efficient. Decisions at the algorithmic, architecture and circuit level can affect power, delay and latency. At this project we are concentrating on low power design. In particular we are revisiting many of arithmetic operations in a different light. Circuits such as multiplier- accumulator that is an essential part of many signal processing applications is studied in detail. New floating point architecture for division is being developed. Constant coefficient multipliers have been re-visited for low power. A high level synthesis tool that can produce a scalable multiplier-accumulator for implementation of these algorithms is written. Owing to the lack of full control over all possible choices of low power design, the design efforts are concentrated towards achieving power economy by choosing appropriate architectures, number system, and algorithms. For example, Residue Number System is used for multiplication and addition. New theories are being developed to take advantage of this carry free system to reduce power. Circuits are being developed for Residue to Binary system to make this class of arithmetic operation more attractive

Collaboration au sein du ReSMiQ

Cowan, Glenn - Université Concordia
Savaria, Yvon - Polytechnique Montréal
Sawan, Mohamad - Polytechnique Montréal

Collaboration hors ReSMiQ

Al-Khalili, D.- Royal Military College
Lynch, B.- Concordia university


Université Concordia
Département de génie Électrique et d'Informatique
1455, Boul. De Maisonneuve O. bureau EV5.111
Montréal (Québec) H3G 1M8
Téléphone: (514) 848-2424 poste 3119
Télécopieur: (514) 848-2802
Adresse de courrier électronique: asim@ece.concordia.ca