Titre: Understanding Ultra‐Low Power VLSI Design: from Basics to Cutting‐Edge Techniques in a Unitary Framework
Conférencier: Massimo Alioto , Dep. of Information Engineering, University of Siena, Italy
Lieu: École Polytechnique de Montréal, Pavillon Lassonde, M-1010 ,
Date et heure:
vendredi le 29 avril 2011 de 08:30 à 16:30

Résumé: In the last few years, subthreshold VLSI circuits have become very popular in ultra‐low power applications such as distributed sensing, wearable computing, biomedical devices, green electronics. These applications typically constrain the power budget to a few μWs and the supply voltage to a few hundreds of mV. Operation at such low power/voltage poses many interesting problems and challenges, and at the same time offers new opportunities to develop emerging applications, as well as to stimulate and enable new technologies and markets. In this seminar, basic concepts and advanced techniques in the ultra‐low power (ULP) VLSI domain, as well as opportunities and challenges, are presented. Although ULP design is still a young field and far from being a well‐established topic, this seminar aims to build strong foundations based on few simple principles, coherently develop advanced concepts and deeply understand cutting‐edge techniques. The seminar is organized as follows. Typical design constraints in ULP systems are preliminarily discussed to understand the context. New design‐oriented transistor and circuit models for ultra‐low voltage (ULV) VLSI circuits are given to develop an intuitive sense of how subthreshold CMOS logic gates work, as well as to build tools that help in managing multiple design tradeoffs at higher levels of abstraction. Issues in ULV VLSI circuits and systems are presented for the first time in a unitary framework that can be applied to very general design cases, in order to develop a coherent perspective on the problems arising in ULP systems and the related solutions. The role of process/voltage/temperature variations will be also understood through simple models and their impact on design will be clarified. Usual misconceptions and incorrect beliefs are thoroughly discussed as well. The degradation of the DC behavior of standard CMOS cells is discussed in depth for the first time, and practical voltage limits are derived. Process/voltage/temperature variations and leakage are analyzed in a consistent framework to show how they ultimately affect voltage scaling and energy minimization. The dependence of the minimum‐energy point on design parameters is also analyzed at many levels of abstraction, from process to layout, circuit and micro‐architecture level. Other than exploring the energy/voltage boundaries of CMOS VLSI circuits, circuit design methodologies to push down the voltage lower bound in standard cell libraries are discussed. For the first time, robustness and yield are considered as further dimensions in the design space. In particular, the seminar aims to clarify the important role (usually neglected) that the voltage lower bound plays in real VLSI circuits, and its relation with the optimal voltage that minimizes the energy consumption. Some recent research results are also presented and new directions for further research are introduced. For example, MOS Current Mode Logic (MCML) circuits are explored as an alternative to standard voltage‐mode CMOS logic styles. Design issues arising in the ultra‐low power realm with power consumption in the order of pW‐per‐gate are discussed, and appropriate circuit techniques to allow reliable operation are introduced.

Note biographique: Massimo Alioto (M’01–SM’07) was born in Brescia, Italy, in 1972. He received the laurea degree in Electronics Engineering and the Ph.D. degree in Electrical engineering from the University of Catania (Italy) in 1997 and 2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dell’Informazione (DII) of the University of Siena as a Research Associate and in the same year as an Assistant Professor. In 2005 he was appointed Associate Professor of Electronics, and was engaged in the same faculty in 2006. In the summer of 2007, he was a Visiting Professor at EPFL ‐ Lausanne (Switzerland). In 2009‐2011, he is Visiting Professor at BWRC – UCBerkeley, investigating on next‐generation ultra‐low power circuits and wireless nodes. Since 2001 he has been teaching undergraduate and graduate courses on advanced VLSI digital design, microelectronics and basic electronics. He has authored or co‐authored more than 160 publications on journals (55+, mostly IEEE Transactions) and conference proceedings. Two of them are among the most downloaded TVLSI papers in 2007 (respectively 10th and 13th). He is coauthor of the book Model and Design of Bipolar and MOS Current‐Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include the modeling and the optimized design of CMOS high‐performance, low‐power and ultra low‐power digital circuits, arithmetic and cryptographic circuits, interconnect modeling, design/modeling for variabilitytolerant and low‐leakage VLSI circuits, circuit techniques for emerging technologies. He is the director of the Electronics Lab at University of Siena (site of Arezzo). Prof. Alioto is an IEEE Senior Member and a member of the HiPEAC Network of Excellence. He is the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society, for which he is also Distinguished Lecturer. He is regularly invited to give talks and tutorials to academic institutions, conferences and companies throughout the world. He serves or has served as a member of various conference technical program committees (ISCAS, ICCD, PATMOS, ICM, ECCTD, CSIE) and Track Chair (ISCAS, ICCD, ICECS, ICM). He was Technical Program Chair of the conference ICM 2010. He serves as Associate Editor of the IEEE Transactions on VLSI Systems, as well as of the Microelectronics Journal, the Integration – The VLSI journal, the Journal of Circuits, Systems, and Computers, the Journal of Low Power Electronics and Applications and the ACM Transactions on Design Automation of Electronic Systems. He was Guest Editor of the Special Issue “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers (2010), and Technical Program Chair for the ICM 2010 conference.

Références: Mots clefs

Ultra‐low power, minimum‐energy computing, subthreshold CMOS logic, VLSI design, MOS Current Mode Logic, PVT variability, energy‐scavenged systems, nodes with perpetual operation.

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