Titre: Scaling Friendly Radio design for SoC
Conférencier: Yorgos Palaska , Intel, É.-U.
Lieu: École Polytechnique de Montréal, Pavillon Lassonde, L-2708 ,
Date et heure:
lundi le 22 avril 2013 de 13:00 à 14:00

Résumé: Integration of the Power Amplifier along with the rest of the radio is compelling since it eliminates expensive external components and enables powerful co-optimizations with the rest of the radio/SoC. Power amplifier design, however, is very challenging in nanoscale CMOS due to the low breakdown voltages, low quality passives, harmful interaction with the RFIC, package and thermal implications, etc. The first WLAN integrated power amplifiers operated in class-AB mode and achieved low modulated efficiencies of <10%, which means that most of the DC power was actually converted to heat. Since then CMOS PAs have come a long way. Linearization techniques, e.g. predistortion, have allowed significant efficiency improvements in conventional class-AB PAs. A number of works have also revisited older PA techniques, e.g. outphasing, polar, etc, and properly adapted them to take advantage of fast transistors and integration available in an SoC. As an example of these new trends, the talk will present an outphasing WLAN power amplifier implemented using CMOS inverters and transformer combining. The transistors here operate as switches, much like in a digital circuit, hence no accurate RF models are required, as demonstrated by a fabricated 32nm prototype. Even more importantly, the PA performance is expected to improve with further CMOS scaling, contrary to conventional PAs. The talk will conclude with survey with other upcoming techniques that promise the next performance improvements in nanometer CMOS power amplifier design.

Note biographique: Yorgos Palaskas (S’98, M’02, SM’11) received the Diploma in Electrical and Computer Engineering from the National Technical University of Athens, Greece, in 1996, and the M.S. and Ph.D. degrees, both in Electrical Engineering, from Columbia University, New York, in 1999 and 2002, respectively.
Since 2003 he has been with Intel Labs, Hillsboro, Oregon, where he is currently an engineering manager. During 2003-2005 he worked on integrated MIMO transceivers and power amplifiers for WiFi. Since 2006 he has been leading research projects on scaling-friendly, SoC compatible, WiFi-WiMAX radios in heavily scaled CMOS processes, and also research on 60GHz radios for multi-Gb/s wireless communications. He has authored and co-authored more than 40 papers at IEEE journals and conferences, 1 book chapter, and has 16 patents issued and several pending.
He is currently serving on the Technical Program Committee for the IEEE International Solid-State Circuits Conference and the IEEE European Solid-State Circuits Conference.

Voyez tous les cour intensifs