David, Jean-Pierre

Professor David conducts research in the field of hardware-software logic system synthesis and their applications, particularly in signal processing and cryptography. In particular, he specializes in programming reconfigurable systems such as FPGAs or others from a high-level description.

A reconfigurable system is a programmable logic circuit whose behavior will be determined at the time of its programming. Today, these circuits integrate several processor cores, hundreds of memories, hundreds of multipliers, tens of thousands of programmable logic functions, multiple dedicated resources and a huge network of configurable connections allowing these resources to be interconnected to create a complex and highly parallel circuit. They increasingly compete with dedicated circuits of the /ASIC/ type because they can be reprogrammed at will and their density now reaches tens of millions of equivalent logic gates.

Reconfigurable circuits fall under both Electrical Engineering (GE) and Software Engineering (SE). Once the physical circuit is built (GE), it still needs to be programmed (SE). However, programming is used to implement a circuit with logic signals that propagate in a manner similar to what happens in a traditional logic circuit (GE). Finally, these circuits often contain one or more processors that need to be programmed (SE). The two fields are therefore very closely related and it becomes necessary to have a broader vision that brings together the two disciplines.

Our main research program, funded by NSERC, consists of developing a new Hardware Description Language (HDL) with an intermediate level of abstraction between the programming languages used in GL and the hardware description languages used in GE. We aim to describe circuits at the functional (algorithmic) level and develop a compiler (CASM) capable of transforming this description into a circuit automatically and safely by construction. In summary, our language allows to describe networks of algorithmic machines that process and exchange data tokens in parallel, somewhat on the model of CSP (Communicating Sequential Processes) and SDL (Specification and Description Language). A major novelty compared to traditional ASM (Algorithmic State Machine) consists of the possibility of making state calls (and therefore returns) in a manner similar to a method call in software or a continuation in functional languages. It then becomes possible to synthesize recursive machines, which allowed us, for example, to implement a version of the QuickSort algorithm (a highly recursive quick sorting algorithm) on FPGA very easily. In addition, the tool automatically generates all the control signals for synchronizing the sending and receiving of data tokens throughout the network without losing any clock cycle (possibly in the form of a continuous pipeline). The designer can therefore focus on the algorithmic aspects and delegate the task of realizing the circuit to the compiler. However, the informed user is aware of the architecture that will be synthesized and can, in the way he describes the algorithm, influence it.

Our research program will soon expand to the possibility of dynamically configuring a reconfigurable circuit. In the same way that a processor can generate the code that it will execute a little later (JIT compilation), we want to explore how a reconfigurable circuit could efficiently generate the circuit that will work a little later on a dedicated task. We will mainly explore how to integrate this functionality into our CASM language and its compiler.