Swamy, Srikanta MN

Signal processing algorithms with ASIC and FPGA implementations

This program concerns various signal processing algorithms and their ASIC and FPGA implementations, as well as the development of high-speed, low-power mixed-mode CMOS digital circuits. Based on the residual number system, algorithms for the design of efficient FIR filters and chaos encoders/decoders are being developed. They will be implemented using ASIC and FPGA techniques. An adaptive Viterbi using strongly connected trellis decoding of binary convolutional codes is being developed. An FPGA implementation of the proposed algorithm will be made based on a systolic array architecture to validate the specifications of the Viterbi encoder prototype. Another subproject of this program aims to develop current-mode filters from well-known voltage-mode filters and implement them using ASIC techniques.