Zilic, Zeljko

Critical Components for SoCs The objective of this project is to develop CAD tools and system design methodologies that would address some of the urgent needs in building scalable and energy-efficient SoCs. First, clock management techniques and circuits are investigated, with a focus on low-power applications. Innovative clock managers, including dynamic clock dividers and reconfigurable VCOs, will be constructed. System-level design methodologies for using dynamically controlled clocks will be examined. Second, the substrate coupling problem will be addressed. We will develop a Voronoi tessellation-based macromodel, construct active methods for interference suppression, and produce several experimental circuits to measure the coupling and validate the developed models. Third, embedded memories will be optimized in terms of yield, reliability, and testability. The optimal solution will be built in silicon. Fourth, integrated network processing cores will be designed. An FPGA-based implementation optimized for IP over SONET/ATM, using the Multiprotocol Label Switching (MPLS) protocol, will be built.