Avec le concours du programme des « Distinguished Lecturerer » de la société IEEE SSCS
Davide Tonietto
Huawei Canada
Date : 8 mai 2026
Hour : 10h30
Place : Université Concordia, Pavillon EV, salle EV2.184, 1515 rue Ste-Catherine Ouest, Montréal
Summary: Explosive computing growth fueled by the AI revolution is putting enormous pressure on energy efficiency. As number of cores and connection bandwidth increases exponentially, serial links are becoming the #1 energy expenditure. It is estimated that serial links consume between 30% and 60% of the total computing & switching power. Besides being an overall energy consumption problem, this brings a variety of architectural challenges, such as the power delivery and heat
dissipation management.
Part 1: The basics of serial link efficiency
What is serial link efficiency? What does it depend on? Is it actually improving? Is it better to go wide-slow or narrow-fast? Does it always pay off to reduce the number of “hops” in a link? I will explain in the simplest terms why I think it is time for a drastic change in what we do to increase interconnect bandwidth and why commonly talked about approaches to improve efficiency will not work as well as advertised. To understand efficiency, we have to dig deep into SerDes historical evolution and how various factors affected efficiency and complexity and how they are related.
Part 2: SerDes power scaling
One of the reasons contributing to the rapid increase of serial link power consumption is the inability of most SerDes to adapt significantly their power consumption to the requirements of the channel they operate on. Most ASICs are built with only one type of long reach (LR) SerDes on die but in a real system they will operate on a vast variety of backplane, chip to chip or chip to module links that vary enormously in complexity from XSR (Extra Short Reach) to VSR (Very Short Reach) to LR. However, most SerDes can only marginally adjust their consumption and this is achieved by a static, manual and error prone process. Therefore, most links use more energy than necessary. I will present a fully automatic power management system that can dynamically reduce a DSP based LR SerDes consumption in excess of 50% depending on channel requirements.
Biographical note: Davide Tonietto is Huawei Fellow & Founder of Hisilicon Serial Link Team (A.K.A. HiLink), with Huawei Technologies Canada since 2011. He was responsible for Hisilicon SerDes IP technology roadmap definition, execution and integration from 2011 to 2021. Over this period of time his organization provided SerDes for over 200 high performance ASICs with data rates ranging from 10 to 112Gbps for applications in Networking, DC, AI, HPC, Wireless infrastructure and Mobile. He holds more than 20 US patents and co-authored several papers on SerDes and wireline communication. His current focus is on improving interconnect efficiency by increasing parallelism, flexibility and decreasing data rate and complexity.
