Pluggable Optics Are Alive and Well

Date: 8 juin 2026
Heure: 10h00
Lieu: Université Concordia, Pavillon EV, salle EV11.119, 1515 rue Ste-Catherine Ouest, Montréal

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Résumé: This talk explores the evolving role of pluggable optics in high-speed data-center interconnects, highlighting why they remain a dominant solution despite emerging alternatives such as co-packaged optics. After introducing the architecture of optical modules and the tradeoffs between pluggable, co-packaged, and scale-out interconnect strategies, the presentation reviews key optical link technologies, including intensity-modulated direct-detect and coherent systems, fiber types, and device implementations such as VCSELs, Mach-Zehnder modulators, and electro-absorption modulators. The talk then examines practical design challenges in modern optical PHYs—such as transmitter performance (e.g., TDECQ), high swing driver design, link budgeting, power constraints, and jitter. Finally, recent advancements in >400 Gb/s per lane direct-detect systems are discussed, illustrating how continued innovation in CMOS, photonics, and system architecture enables scaling to ever higher data rates.

Note biographique: Mike Bichan received his undergraduate degree from the University of Toronto’s Engineering Science program in 2003 and his Ph.D. in Electrical Engineering from the University of Toronto in 2011. He began his career at V Semiconductor, a startup focused on SerDes IP development across multiple foundry technologies including TSMC,
UMC, Samsung, and Intel. Following V Semiconductor’s acquisition by Intel in 2012, he spent 12 years designing high-speed SerDes IP in Intel process technologies, contributing to data rates ranging from 16 Gb/s to 128 Gb/s and supporting a wide range of industry standards including Ethernet, PCI Express, CPRI, JESD, USB, SATA, GPON, HDMI, DisplayPort, OTN, SDI, and SONET. In 2024, he joined Marvell’s Optical PHY group, where he works on CMOS SerDes solutions for pluggable optical modules targeting data rates of 200 Gb/s and 400 Gb/s per lane. He is an author of several publications in high-speed I/O design, including work on PCIe Gen5 SerDes, multi-protocol PAM-4 receivers, and next-generation networking SoCs.