Swamy, Srikanta M. N.
Université Concordia
Membre régulier
Description du programme de recherche
Signal Processing Algorithms with ASIC and FPGA Implementations
This program is concerned with various signal processing algorithms and their ASIC and FPGA implementations as well as the development of high speed low-power CMOS mixed-mode digital circuits. Based on the residue number system, algorithms for the design of efficient FIR filters and chaos encoders/decoders are being developed. These will be implemented using ASIC and FPGA techniques. An adaptive Viterbi using strongly connected trellis decoding of binary convolution codes is being developed. An FPGA implementation of the proposed algorithm will be carried out based on a systolic array architecture in order to validate the specifications of the prototype Viterbi coder. Another subproject in this program aims at developing current mode filters from well-known voltage mode filters, and implement them using ASIC techniques.
Coordonnées:
Université Concordia
Département de génie Électrique et d'Informatique
1455, Boul. De Maisonneuve O.
Montréal (Québec) H3G 1M8
Canada
Téléphone: (514) 848-2424 poste 3091
Télécopieur: (514) 848-2802
Adresse de courrier électronique: swamy@ece.concordia.ca