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Titre: IBM Physical Synthesis and Routability-Driven Timing Closure
Conférencier: Cliff Sze , IBM Austin Research Laboratory, Texas, É.-U.
Lieu: Université Concordia, EV-Ingineering complex, Salle EV2.184 ,
Date et heure: jeudi le 25 octobre 2012 de 17:00 à 19:00

Résumé: It is well-known that scaling of VLSI feature size has shifted the EDA research focus from logic synthesis to physical design. In the last decade, some researchers claimed that logic synthesis is dead and (placement centric) physical synthesis has gained great popularity. It is obvious that wire delay dominates the total path delay, and therefore, placement becomes the most critical factor to timing yield. However, some EDA researchers may not observe the evolving real challenge for timing closure in the latest technology nodes -- the routability problem.
When hierarchical methodology and SOC designs becomes the mainstream, placement blockages are pervasive in the layout and thick wires are inevitable for global (or even local) interconnects. This greatly reduces the number of available wiring tracks. Unfortunately, scaling led to an ever-increasing demand on routing resource. ,This combination became a perfect storm for routability, which results in wire detours and becomes a brick wall for timing closure. In this talk, I will detail the routability problem in the industry and explain the latest research in routing, and routability-driven timing-driven flow.

Note biographique: Cliff Sze is a research staff member at the IBM Austin Research Laboratory, Austin, Texas, where he focuses on integrated placement, routing and timing optimization for ASIC and microprocessor designs. Cliff has contributed to several IBM ASIC designs, as well as POWER 6, POWER 7, Xbox 360 and the Sony/Toshiba/IBM CELL processors for PlayStation consoles. He received several IBM technical/invention awards, filed more than 20 patents applications and was granted 10+ patents worldwide. His research interests include design and analysis of algorithms, computer-aided design technique for very large scale integration, physical design, and performance-driven interconnect synthesis. He received his B.Eng. and M.Phil. degrees from the Department of Computer Science and Engineering, the Chinese University of Hong Kong and his Ph.D. degree in computer engineering at the Department of Electrical Engineering, Texas A&M University. Dr. Cliff Sze has been actively serving the academic/research community, for example, on the program committees for ICCAD, ASPDAC, ISPD, SLIP, SOCC, and as a reviewer for top journals such as IEEE TCAD, IEEE TVLSI as well as IEEE TCAS. He also has served as a mentor for several SRC projects, as the program chair of International Symposium on Physical Design 2013, as the contest chair of the global routing and clock network synthesis contests in ISPD (2008-2010) and as the Computer-Aided Network Design track chair for ISCAS 2011 and 2012. Dr. Sze was the recipient of the ACM/SIGDA Technical Leadership Award and the IEEE/ACM Design Automation Conference Graduate Scholarships. In order to promote EDA research and industry-academia collaboration, he has given more than 15 invited talks to the top universities worldwide.

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